1. Field of the Invention
The present invention relates to a clock generation circuit, suitable to be integrated in a microprocessor, for multiplying a frequency of an input clock to output it and a semiconductor device comprising the clock generation circuit, and more particularly to an improvement technique to reduce a time period until a stable output clock is obtained.
2. Description of the Background Art
A clock generation circuit having a PLL (Phase Locked Loop) circuit outputs a clock in synchronization with an input clock (synchronous clock) or a clock obtained by multiplying the input clock (multiplied clock). A recent microprocessor, which operates in synchronization with a high-speed clock of several tens to several hundreds MHz, necessarily incorporates the clock generation circuit for outputting the multiplied clock.
A background-art PLL circuit is an analog-type one, which comprises a voltage control oscillator (VCO) and controls a capacitor voltage for holding a control voltage of the VCO with a charge pump to control an oscillation frequency. The analog PLL circuit, however, has problems of being hard to control under a low power supply voltage, low noise immunity, requiring a long time period to achieve a stable operation (i.e., a long lock period), and taking a time to resume an operation when the oscillation of the PLL circuit is stopped by stop of the input clock. To solve these problems, some PLL circuits with digital delay line have been revealed.
FIG. 20 is a block diagram showing a configuration of a background-art clock generation circuit 151. The clock generation circuit 151 is revealed in "Development of Full Digital PLL for Lower Voltage" by Kouichi Ishimi and two others: "Shingakugihou", Vol. 97, No. 106, pp. 29 to 36, June, 1997, which comprises a PLL circuit 70 and a buffer 73. The PLL circuit 70 is a digital-type one, comprising a multiplier circuit 71 and a phase synchronous circuit 72. The multiplier circuit 71 multiplies a frequency of an input clock IN to output a multiplied clock N-OUT. The phase synchronous circuit 72 delays the multiplied clock N-OUT by a certain amount of delay (delay time) to output it as an output clock PLL-OUT.
The output clock PLL-OUT is output as an output clock PHI through the buffer 73. The output clock PHI is supplied for other circuits which operate in synchronization therewith. The output clock PHI is further fed back to the phase synchronous circuit 72. The phase synchronous circuit 72 compares the input clock IN with the fed-back output clock PHI in phase and determines the amount of delay of the output clock PLL-OUT with respect to the multiplied clock N-OUT so that the phase difference may be cancelled. That produces a clock in synchronization with the input clock IN, with its frequency multiplied, as the output clock PHI.
FIG. 21 is a block diagram showing an internal configuration of the multiplier circuit 71. The multiplier circuit 71 comprises a digital delay line 75, a delay fine-tuning circuit 76, an OR circuit 80 and a ring oscillator including an AND circuit 81. The digital delay line 75 is configured as a variable delay circuit, comprising a plurality of delay elements which can be selectively cascaded. The amount of delay can be changed step by step, in proportion to the number of cascaded delay elements. The delay fine-tuning circuit 76 is configured as the same variable delay circuit. The amount of change in the amount of delay for one step is determined smaller in the delay fine-tuning circuit 76 than in the digital delay line 75.
Thus, the amount of delay is variable in the ring oscillator. Further, the ring oscillator is configured as such a negative feed-back loop as to invert the level of a signal in a single cycle along the loop. The ring oscillator therefore oscillates, and half of the oscillation cycle, i.e., half cycle, corresponds to the amount of delay in the single cycle.
A phase comparator 79 compares a delay clock DL-OUT obtained from an output of the delay fine-tuning circuit 76 included in the ring oscillator (precisely, a clock obtained by dividing the delay clock DL-OUT by its multiplication ratio) with the input clock IN in phase, and increments a count value of a digital counter 78 when the former phase gets behind and conversely decrements the count value when gets ahead. When the phases coincide with each other, the count value is kept constant.
The digital counter 78 inputs its count value into the digital delay line 75 and the delay fine-tuning circuit 76. The total amount of delay of the digital delay line 75 and the delay fine-tuning circuit 76 thereby changes proportionally to the count value. Thus, the amount of delay of the ring oscillator is controlled so that the phase of the delay clock DL-OUT may coincide with that of the input clock IN.
Based on the input clock IN and the delay clock DL-OUT, a control unit 82 transfers a signal DL-SET to the OR circuit 80 and a signal DL-ACT to the AND circuit 81. That produces the multiplied clock N-OUT as a clock signal having a predetermined multiplication ratio with respect to the input clock IN.
FIG. 22 is a timing chart showing an operation of the multiplier circuit 71. At a rise of the input clock IN corresponding to the start of one clock cycle of the input clock IN, the control unit 82 asserts (activates) the signal DL-ACT. The multiplied clock N-OUT thereby changes from a low level to a high level. As a result, the delay clock DL-OUT changes from a low level to a high level at the time when the delay clock DL-OUT is delayed by the amount d of delay corresponding to the amount of delay of the ring oscillator (more exactly, the total amount of delay of the digital delay line 75 and the delay fine-tuning circuit 76).
The control unit 82 asserts the signal DL-SET only in the time period from the rise of the input clock IN to the first rise of the delay clock DL-OUT after that, and negates (normalizes) it in other period. At the time when the multiplied clock N-OUT completely outputs pulses of which number corresponds to a predetermined multiplication ratio from the rise of the input clock IN, the control unit 82 negates the signal DL-ACT. FIG. 22 shows a case where the multiplication ratio is four.
As a result, at every rise of the input clock IN, four pulses are output as the multiplied clock N-OUT. As shown in FIG. 22, when the fourth phase of the delay clock DL-OUT comes earlier because the amount d of delay is smaller than an appropriate amount, the count value of the digital counter 78 is incremented by one every one clock cycle of the input clock IN so as to delay the phase. As a result, pulse widths of the delay clock DL-OUT and the multiplied clock N-OUT increase and then the delay clock DL-OUT and the input clock IN coincide with each other in phase (in other words, the multiplier circuit 71 comes into a lock state).
When the amount d of delay is larger than the appropriate amount, conversely, the count value is decremented by one so as to make the phase earlier. That achieves the lock state. In the lock state obtained is a clock with its frequency multiplied by a predetermined multiplication ratio of the frequency of the input clock IN, as the multiplied clock N-OUT.
FIG. 23 is a block diagram showing an internal configuration of the phase synchronous circuit 72. In the phase synchronous circuit 72, the multiplied clock N-OUT goes through a delay line 87, a delay line 88 and an output selector 90 in this order, or through the delay line 87, a fixed delay circuit 89 and the output selector 90 in this order, to be delayed by a certain amount of delay and output as the output clock PLL-OUT. The output selector 90 selects one of two delay paths. The delay lines 87 and 88 are digital-type ones.
A phase comparator 85 compares the output clock PHI with the input clock IN in phase, and decrements a count value of a digital counter 86 when the former phase gets behind and conversely increments the count value when gets ahead. When the phases coincide with each other, the count value is kept constant. The digital counter 86 inputs its count value into the digital delay lines 87 and 88. The total amount of delay of the digital delay lines 87 and 88 thereby changes proportionally to the count value.
FIG. 24 is a timing chart showing an operation of the phase synchronous circuit 72. As shown in FIG. 24, when the phase of the output clock PHI gets ahead of that of the input clock IN because the amount D of delay of the output clock PHI with respect to the multiplied clock N-OUT is smaller than an appropriate amount, the count value of the digital counter 86 is incremented by one every one clock cycle of the input clock IN so as to delay the phase of the output clock PHI. As a result, the phase of the output clock PHI is delayed by an increase in the amount D of delay and then coincides with the phase of the input clock IN (in other words, the phase synchronous circuit 72 comes into a lock state).
When the phase of the output clock PHI lags behind that of the input clock IN, conversely, the count value is decremented by one so as to make the phase earlier. That achieves the lock state. Thus, since a control is made so that the phase of the output clock PHI coincides with that of the input clock IN, the clock obtained as the output clock PHI is in synchronization with the input clock IN and multiplied by a predetermined multiplication ratio.
The background-art clock generation circuit 151, however, has the following problems. First, the multiplier circuit 71 has a problem of taking a long time to achieve a lock state. For example, in a typical case where the digital counter 78 is a 10-bit counter (with its count value in 10-bit representation) required is a time period of 2.times.2.sup.10 =2048 clock cycles at the maximum.
If the lock period is longer, there is a longer waiting time by the lock period until a semiconductor device supplied with the output clock comes back to a normal operation. In cases, for example, where the frequency of the output clock (, the frequency of the input clock, the multiplication ratio or the like) is changed during an operation, or where the oscillation of the multiplier circuit 71 is stopped when the semiconductor device is in a low-power mode and then the oscillation of the multiplier circuit 71 is resumed when the semiconductor device is brought back into a normal operation mode. When the operation frequency of the semiconductor device is often changed or the low-power mode is often used, especially, there arises a disadvantage in terms of performance and power consumption.
The phase synchronous circuit 72 also has a problem of taking a long time to achieve a lock state. For example, in a typical case where the digital counter 86 is an 8-bit counter required is a time period of 2.times.2.sup.(8-1) =256 clock cycles at the maximum as the lock period.
In the clock generation circuit 151, after the device comes into the lock state, the multiplier circuit 71 and the phase synchronous circuit 72 operate independently. Therefore, if the cycle of the multiplied clock N-OUT slightly varies with temperature variation, voltage variation or a noise, a phase difference arises between the output clock PLL-OUT and the input clock IN. FIG. 25 is a timing chart showing this operation. As illustrated in FIG. 25, when the cycle of the multiplied clock N-OUT becomes shorter (in other words, the frequency becomes higher) under some influence, the phase of the output clock PLL-OUT consequently goes ahead (time t41).
At this time, the multiplier circuit 71 increases the amount of delay of the delay lines 75 and 76 to enlarge the cycle of the multiplied clock N-OUT. At the same time, the phase synchronous circuit 72 increases the amount of delay of the delay lines 87 and 88 so that the phase of the output clock PLL-OUT may coincide with that of the input clock IN. Though the phase difference between the output clock PLL-OUT and the input clock IN can be cancelled only if the cycle of the multiplied clock N-OUT becomes normal again, since the multiplier circuit 71 increases its amount of delay, the phase of the output clock PLL-OUT lags behind that of the input clock IN at the next clock cycle (time t42).
Thus, there is a problem of jitter in the phase difference between the output clock PLL-OUT and the multiplied clock N-OUT, which is caused by independent controls of the multiplier circuit 71 and the phase synchronous circuit 72 over the amount of delay. When the jitter occurs, both the multiplier circuit 71 and the phase synchronous circuit 72 come into the lock state again, requiring a long time to obtain a stable output clock PLL-OUT.